HDL Front-Ends

Interra Systems has production-proven expertise in developing HDL Front-Ends. Interra markets analyzers for Verilog, SystemVerilog, VHDL, UPF, CPF, Spice and several other EDA standards. Latest standard compliant and easy to use building blocks from Interra Systems enable users to reduce time-to-market by saving a significant amount of development time. Interra’s customers include top-tier EDA vendors, EDA startup companies and internal CAD groups of SoC companies. EDA Tools that integrate Interra’s EDA Objects are in production-use on thousands of chip designs. Interra ensures its front-ends keep pace with language enhancements, capacity and quality requirements.

System Verilog AnalyzerCheetah is a full language Verilog and SystemVerilog Front-End Analyzer. It fully supports following standards:

  • System Verilog: IEEE-1800-2012, IEEE-1800-2009, IEEE-1800-2005
  • Verilog: IEEE-1364-2005, IEEE-1365-2001, IEEE-1364-1995, OVI 2.0
  • PSL: IEEE-1850 - support for both embedded and external verification units

Cheetah parses all versions of standards of SystemVerilog and Verilog and creates an in-memory Object Model. Applications can then access the design information instantly using efficient generic programming interface. Standard compliant and easy to use building blocks from Interra Systems enable users to reduce time-to-market by saving a significant amount of development time.

Front-end analyzers from Interra Systems are widely used by top-tier EDA tool developers as a universal front-end to their design solutions. Interra’s customers include top-tier EDA vendors, EDA startup companies and internal CAD groups of SoC companies. EDA Tools that integrate Interra’s EDA Objects are in production-use on thousands of chip designs.

Interra ensures its front-ends keep pace with language enhancements, capacity and quality requirements.

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Key Features
  • Latest support of Language standards
  • Option to comply with any of supported standards
  • Comprehensive syntax and semantic checks
  • New Generic Programming Interface for efficient EDA application development
    • Compile time type-safety helps catch errors early
    • Usage of high level design patterns makes application code more concise
    • Separation of flow and actions to make EDA tool development more maintainable
  • Editable and Extensible object model
  • RTL subset semantics checks
  • Browser and decompilation utility for easy debugging
  • Utility Objects for Expression Evaluation, Elaboration and Partial analysis
  • Highly customizable - error handler, user-defined attributes, user-defined meta comments, and more

VHDL Analyzer Jaguar is a full language VHDL Front-End Analyzer. It fully supports following standards:

  • VHDL: IEEE-1076-2008, IEEE-1076-2002, IEEE-1076-1993, IEEE-1076-1987
  • PSL: IEEE-1850-2005, V1.1 and V1.01

Jaguar parses all versions of standards of VHDL and creates an in-memory Object Model. Applications can then access the design information instantly using efficient generic programming interface. Standard compliant and easy to use building blocks from Interra Systems enable users to reduce time-to-market by saving a significant amount of development time.

Front-end analyzers from Interra Systems are widely used by top-tier EDA tool developers as a universal front-end to their design solutions. Interra’s customers include top-tier EDA vendors, EDA startup companies and internal CAD groups of SoC companies. EDA Tools that integrate Interra’s EDA Objects are in production-use on thousands of chip designs.

Interra ensures its front-ends keep pace with language enhancements, capacity and quality requirements.

Download Datasheet

Key Features
  • Latest support of Language standards
  • Option to comply with any of supported standards
  • Comprehensive syntax and semantic checks
  • Language compliant library management for incremental compilation
  • Capability to scan and sort based on analysis order
  • New Generic Programming Interface for efficient EDA application development
    • Compile time type-safety helps catch errors early
    • Usage of high level design patterns makes application code more concise
    • Separation of flow and actions to make EDA tool development more maintainable
  • Editable and Extensible object model
  • RTL subset semantics checks
  • Browser and decompilation utility for easy debugging
  • Utility Objects for Expression Evaluation, Elaboration and Partial analysis
  • Highly customizable - error handler, user-defined attributes, user-defined meta comments, and more

MixedHDL - Mixed Language Design Elaborator Most of the complex SoC designs today use one or more of Verilog, SystemVerilog and VHDL to implement various sub-systems. EDA tool developer needs to provide support for mixed language parsing.

MixedHDL from Interra Systems uses Cheetah, the Verilog and SystemVerilog front-end analyzer and Jaguar, the VHDL front-end analyzer to bring MixedHDL capability for EDA tool developers. Programming layer of MixedHDL analyzes mixed designs and elaborates cross-HDL instances. EDA tool developers can bring mixed-language support to their tool quickly. Language specific functionality is available through Cheetah and Jaguar API layer.

MixedHDL supports following EDA standards:

  • SystemVerilog: IEEE-1800-2012, IEEE-1800-2009, IEEE-1800-2005
  • Verilog: IEEE-1364-2005, IEEE-1365-2001, IEEE-1364-1995, OVI 2.0
  • VHDL: IEEE-1076-2008, IEEE-1076-2002, IEEE-1076-1993, IEEE-1076-1987
  • PSL: IEEE-1850-2005, V1.1 and V1.01

MixedHDL in conjunction with Cheetah and Jaguar parses all versions of standards of Verilog, SystemVerilog and VHDL and creates an in-memory Object Model. Applications can then access the design information instantly using efficient generic programming interface. Standard compliant and easy to use building blocks from Interra Systems enable users to reduce time-to-market by saving a significant amount of development time.

Front-end analyzers from Interra Systems are widely used by top-tier EDA tool developers as a universal front-end to their design solutions. Interra’s customers include top-tier EDA vendors, EDA startup companies and internal CAD groups of SoC companies. EDA Tools that integrate Interra’s EDA Objects are in production-use on thousands of chip designs.

Interra ensures its front-ends keep pace with language enhancements, capacity and quality requirements.

Download Datasheet

Key Features
  • Latest support of language standards through Cheetah and Jaguar
  • Configurable Elaborator
    • Light weight single level step-by-step elaboration
    • Static elaboration of the whole design
  • Static elaboration provides for
    • Uniquification
    • Unrolling
    • Multi-level scope variable resolution
    • Multi-level defparam propagation
    • Resolution of parameter/generic overrides
    • Semantic check for elaborated object model
  • New Generic Programming Interface for efficient EDA application development
    • Compile time type-safety helps catch errors early
    • Usage of high level design patterns makes application code more concise
    • Separation of flow and actions to make EDA tool development more maintainable

Netlist Object ModelNOM is a language-independent front-end for Netlist applications. It analyzes Verilog, VHDL and EDIF netlists and creates a language neutral Object Model for connectivity. Applications can then access the design information in the Object Model using common Programming Interface, thus saving enormous time and resources. Rather than spending time writing parsers and multiple front-ends for different language inputs, designers can now spend time designing their solutions.

Extensive customization capabilities allow EDA tool developers to extend and mould NOM as per their needs. NOM is used as the front-end for a diverse set of EDA applications to increase the speed of development.

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Key Features
  • Readers and writers for Verilog, VHDL and EDIF
  • Dynamic connectivity information model
  • User extensible object model
  • Functions for flattening, parameterization, and expression evaluation
  • Intuitive API for language independent front-end development
  • API to access Object Model information
  • Optimized for memory usage and run-time performance

Concorde - Fast SynthesisConcorde creates structural implementation for given Register Transfer Level hardware description in System Verilog, Verilog, VHDL, and mixed languages. This language neutral solution is widely used as front-end for Functional Simulation, Formal Verification, hardware acceleration/emulation, low power applications, and mapping to specialized hardware architectures.

Download Datasheet

Key Features
  • Supports SystemVerilog, Verilog, VHDL, and Mixed Designs
  • Supports Industry standard synthesizable subset
  • Integrates easily as front-end of EDA tools
    • API to access in-memory netlist information
    • Edit APIs both at RTL/Analyzer and netlist level
    • Netlist level Verilog, VHDL output
  • Name mapping information for debug usage
  • Various settings to Control generated Netlist behavior/level
  • Customizability to provide unified look-and-feel
  • Platform support: Solaris 32-bit/64-bit, Linux 32-bit/64-bit

Designed to meet the needs of EDA tool developers, Interra's suite of Standard Language Analyzers provide a memory optimal, robust, and easy-to-integrate front-end for standard languages and formats. Enabling EDA tool developers to concentrate on their core competency, rather than spending time writing parsers, these analyzers save resources and time to market high quality EDA products.


Analyzer Description
SPICE Analyzer Comprehensive support for analysis of Spice netlists, covering all features and constructs. Extensible architecture to support various Spice variants including HSPICE. Feature rich C++ API to modify netlist, evaluate expressions, flatten, elaborate, and decompile. Download Datasheet
UPF Analyzer Supports Accellera standard UPF 1.0, can be easily integrated in TCL and C++ environment Download Datasheet
CPF Analyzer Supports CPF Version Si2 1.1. The object model can be easily accessed using the analyzer's C++ interface enabling seamless integration with C++ based EDA Tools. Download Datasheet
SLF (Liberty) Analzer Supports SLF 2008.09. The object model stores expressions as expression trees, hereby reducing post processing by the applications. Supports Scalable Polynomial Delay and Power Models Download Datasheet
SDF Analyzer Supports SDF 2.0, 2.1, 3.0 and 4.0. Can be customized to store only typical, max, or min delays. Parses 18M lines of SDF in 2 minutes
DSPF/RSPF Analyzer Supports both DSPF and RSPF as per Cadence's SPF version 1.5.1. Effective object model handling of coupling capacitor, name map, and parasitic values. Provides optional callback mechanism for handing application specific needs
VCD Analzer Supports VCD format as defined under IEEE 1364 standard. Provides optional callback mechanism for handling application specific needs
SPEF Analyzer Supports IEEE 1481 standard. Effective object model handling of coupling capacitor, name map, and parasitic values (singlet vs triplet). Capable of handling SPEF that are more than 2 GB in size. Provides optional callback mechanism for handing application specific needs
SAIF Analyzer Supports Synopsys SAIF, version 10.02. Provides optional callback mechanism for handing application specific needs
GDSII Analyzer Fully supports GDSII version 3.0. Provides APIs to access the object model information, such as hierarchy, geometries, and pin information. Provides a comprehensive suite of utilities to save time and reduce development cycle. These utilities include Comparator, Flattener, Viewer, and GDSII-ASCII-GDSII Converter