SoC Design Services

Interra's development and support services to SoC/ASIC/Memory companies cover:

• Circuit Design and Layout
• SoC Verification
• Memory Design and Verification
• Design Methodologies and Flows
• Library Development

Circuit Design and Layout

Stressed product lifecycles and rapidly changing technologies are driving the semiconductor industry and design houses to focus more on their core competencies. Need for quick turn-around and reduced cost require them to work with partners to meet current challenges. In keeping with these needs, Interra offers services in the following areas:

• RTL Development: Development of RTL in Verilog, VHDL, or SystemVerilog from given specifications. Interra follows in-house coding guidelines or guidelines provided by customer to produce readable and maintainable RTL
• IP evaluation, customization, verification, integration and development
• Synthesis of RTL for ASIC/FPGA, RTL-to-netlist verification
• Layout: Auto place & route, design verification, layout extraction, layout-vs-schematic

SoC Verification

SoC verification has now become time consuming and complex for system designers. Verification managers have found that it is good to rely on formal techniques to get an alternate perspective. At Interra, we have experienced a variety of verification environments including assertion based formal methods that provide a sense of completeness. Interra has worked on module-level as well as IP verification using functional and formal methods.

Interra has developed PSL and SVA based Formal Verification suite for following areas:

• DFT protocols
• Chip level power and clock management
• DMA Controller
• Floating point accelerator
• Packet based bus protocols (PCI-XP, SATA, ARM-AMBA, SRIO)
• Audio and Video Decoder

Interra has extensive experience with standard protocols and several customer specific IPs, and has developed formal verification test suites for these IPs in the SoC context.

Interra Advantage

• Ability to understand and analyze protocol specifications
• Knowledge of methodology used for Formal Verification
• Software Verification methodology
• Testbench modeling and transactor development
• Verification methodology migration, such as e to SV

Memory Design and Verification

Memory design and verification services from Interra Systems enable memory designers and ASIC/SoC developers to rapidly converge on their design goals. Interra engineers have designed and verified memories and helped ASIC, SoC and other IC designers embed memory into their designs. Fully verified memories can be provided with multiple views - physical views (GDSII, LEF), logical views (SPICE, Verilog) and timing models (Verilog, VHDL, VITAL, Synopsys) based on custom delay and characterization methodologies. Assistance to create memory compilers is also provided along with integration services for incorporating MC2, the memory development environment, into design flow requirements. Training is also available to users and integrators of the memory development systems.

Memory design and verification services are complimented by Interra's MC2, that provides ability to automate the memory design process for standard and embedded memories. MC2 is used as a platform for seamless migration to new semiconductor manufacturing processes. The platform is also being used for design and distribution of memories and ensuring the reuse of a base design over many generations of processes. Numerous users have also taken advantage of the platform to scale their memory designs to higher densities.

Design Methodologies and Flows

Methodologies and EDA tool flow development, validation, and support services from Interra enable designers to rapidly converge on their design goals and free their time to focus on core competencies. Interra has a strong team of engineers and technical managers who are fully conversant with EDA tools from major industry vendors and have experience in developing and maintaining design and verification flows in ASIC, SOC, and custom design space. Interra has successfully been able to take the ownership of developing, deploying, and supporting design toolkits, and verification methodologies for several major semiconductor organizations. Interra also has the experience in developing point tools to target specific design and verification needs that cannot be met by generic EDA solutions.

Sample projects

• Design toolkit development and support
• Verification methodology development and support
• Validation/Evaluation of CAD tools
• Development and deployment of automatic SoC creation tool
• Toolkit development for DFT methodology and Library development
• Development and support of IP package creation and QC flows

Library Development

ASIC/FPGA design flow and methodologies requires a set of libraries at various levels to make sure all EDA tools work consistently. Interra has extensive experience in working with standard cell, IO libraries, and memory models. In addition, Interra has experience with various EDA tools and library cell views needed by these tools.