Interra Design Automation solutions are led by standards-compliant EDA building blocks (EDA Objects), HDL coverage test suites and Memory development system (MC2). EDA solutions from Interra Systems reduce development time and improve productivity for EDA tool developers and memory designers. Our solutions are widely used by major EDA companies, startups and SoC technology companies.
EDA Objects: Interra Systems has a production-proven expertise in developing front-end language analyzers. Interra markets analyzers for Verilog, SystemVerilog, VHDL, UPF, CPF, Spice and several other EDA standards. Latest standard compliant and easy to use building blocks from Interra Systems enable users to reduce time-to-market by saving a significant amount of development time. Interra’s customers include top-tier EDA vendors, EDA startup companies and internal CAD groups of SoC companies. EDA Tools that integrate Interra’s EDA Objects are in production-use on thousands of chip designs. Interra ensures its front-ends keep pace with language enhancements, capacity and quality requirements.
Verilog, SystemVerilog, VHDL and Mixed Language Front-End now come powered with the new Generic Programming Interface. The new generic programming interface for Interra Analyzers includes compile time type-safety, usage of high level design patterns and separation of flow and actions to make EDA tool development easier and more efficient. It reduces the complexity of classical Object Oriented Programming interfaces, creates better safety over traditional and error-prone runtime type-checking, cuts down on time-to-expertise of intricate use-models. Interra’s generic programming interface results in smaller application source code that enables faster time to market at lower cost of development and maintenance.
Beacon test suites from Interra Systems characterize EDA tools for compliance and coverage across HDL/HVL language constructs and styles. Conforming to industry accepted definition and interpretation of language and synthesis semantics. Interra offers support for various EDA Standards including Verilog-RTL subset, VHDL-RTL subset, SystemVerilog, VHDL-2008, Mixed Language and PSL.
MC2: Memory Development System allows memory designer to define their memory architecture for standard or embedded memories. MC2 can then generate memory instances along with full range of front-end and back-end views. MC2 provides a platform for seamless migration to new processes. By enhancing the overall methodology for the design and distribution of memories, MC2 ensures the reuse of a base design over many generations of sub-micron processes. Numerous users have taken advantage of MC2 capabilities for scaling their memory designs to higher densities, placing memories within their SoC, ASIC or IC designs, and making their memory design process more efficient.
| Product Name | Description |
|---|---|
| Memory Development | |
| MC2 - Memory Development System | Memory Development System for standard and embedded memories |
| EDA Objects | |
Cheetah -
Verilog, SV Front-End |
Complete language front-end for System Verilog applications. Provides access to the parse tree through APIs |
| Jaguar - VHDL Front-End |
Complete language front-end to VHDL applications. Provides access to the parse tree through APIs |
| MixedHDL - Mixed Language Design Elaborator |
Allows analysis of mixed designs that contain Verilog, SystemVerilog and VHDL. |
| Beacon - HDL/HVL Test Suites | Family of test suites for RTL-Verilog, RTL-VHDL, Verilog-2001, Mixed Verilog VHDL, System Verilog, System Verilog Assertions, and PSL |
| Concorde - Fast Synthesis/ Elaborator | Fast RTL Synthesis/elaboration for System Verilog, Verilog, VHDL, and mixed designs. Quick synthesis can be used for verification, acceleration, and estimation purposes |
| NOM - Netlist Front-End | Language independent front-end for netlist applications supporting Verilog, VHDL, and EDIF 200 formats |
| Other Analyzers | Analysis of SPICE, UPF, CPF, SLF, SDF, DSPF/RSPF, VCD, SPEF, SAIF, and GDSII. EDA applications can quickly access data defined in standard languages using APIs |
