MC2 - Memory Development System
MC2 automates the design process for standard and embedded memories. MC2 also provides a platform for seamless migration to new processes. By enhancing the overall methodology for the design and distribution of memories, MC2 ensures the reuse of a base design over many generations of sub-micron processes. Numerous users have taken advantage of MC2 capabilities for scaling their memory designs to higher densities, placing memories within their SoC, ASIC or IC designs, and making their memory design process more efficient.
Key Features
 Memory Description Language (MDL) to create Memory Architecture - Supports spreadsheet based CSV format for specifying tiling information
- Creates Various Views
- Physical Views - GDSII, LEF; Logical Views - SPICE, Verilog
- Timing Models - Verilog, Synopsys, VHDL, ALF
- Data sheet
- Any Proprietary Model Based on Given Template
- Enables Automatic Tiling and Netlisting
- Generates Power Ring/Power Mesh
- Has an integrated and programmable BIST engine
- Provides a Memory Characterization Framework
- Provides an interface to OpenAccess
- Allows Via Programming, Decoder Building, ROM Programming
- Generates Internal Routes
- Contains a delay and power characterization module
- Provides GDS Import for Legacy Memory Designs
- Provides utilities: Tiling Rule Checker, MDL Debugger, Configuration
Coverage
- Encrypts Memory Architecture files for Secure Distribution
- Has a Web interface for instance creation
- Automates interpolation and derating for delay/power numbers for all sizes
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