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Concorde creates structural implementation for given Register Transfer Level hardware description in System Verilog, Verilog, VHDL, and mixed languages. This language neutral solution is widely used as front-end for Functional Simulation, Formal Verification, hardware acceleration/emulation, low power applications, and mapping to specialized hardware architectures.

Key Features

• Supports SystemVerilog, Verilog, VHDL, and Mixed Designs
• Supports Industry standard synthesizable subset
• Integrates easily as front-end of EDA tools
  • API to access in-memory netlist information
  • Edit APIs both at RTL/Analyzer and netlist level
  • Netlist level Verilog, VHDL output
• Name mapping information for debug usage
• Various settings to Control generated Netlist behavior/level
• Customizability to provide unified look-and-feel
• Platform support: Solaris 32-bit/64-bit, Linux 32-bit/64-bit, Windows