

Cheetah
provides a customizable, robust, high performance, and easy to integrate
System Verilog (IEEE 1800-2005) and Verilog (IEEE 1364-1995, 2001, 2005)
parser and elaborator front-end for EDA tools.
Cheetah parses the complete language and creates an in-memory Object Model. Applications can then access the design information instantly, thus saving enormous time and resources. Rather than spending time writing parsers, designers can now spend time designing their solutions. In addition, Cheetah supports PSL (IEEE 1850) analysis for both embedded PSL and external verification units. Cheetah offers control options enabling applications to work with PSL and System Verilog together.