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System Verilog AnalyzerCheetah is a full language Verilog and SystemVerilog Front-End Analyzer. It fully supports following standards:
  • SystemVerilog: IEEE-1800-2009, IEEE-1800-2005
  • Verilog: IEEE-1364-2005, IEEE-1365-2001, IEEE-1364-1995, OVI 2.0
  • PSL: IEEE-1850 - support for both embedded and external verification units

Cheetah parses all versions of standards of SystemVerilog and Verilog and creates an in-memory Object Model. Applications can then access the design information instantly using efficient generic programming interface. Standard compliant and easy to use building blocks from Interra Systems enable users to reduce time-to-market by saving a significant amount of development time.

Front-end analyzers from Interra Systems are widely used by top-tier EDA tool developers as a universal front-end to their design solutions. Interra’s customers include top-tier EDA vendors, EDA startup companies and internal CAD groups of SoC companies. EDA Tools that integrate Interra’s EDA Objects are in production-use on thousands of chip designs.

Interra ensures its front-ends keep pace with language enhancements, capacity and quality requirements.

Key Features

  • Latest support of Language standards
  • Option to comply with any of supported standards
  • Comprehensive syntax and semantic checks
  • New Generic Programming Interface for efficient EDA application development
    • Compile time type-safety helps catch errors early
    • Usage of high level design patterns makes application code more concise
    • Separation of flow and actions to make EDA tool development more maintainable
  • Editable and Extensible object model
  • RTL subset semantics checks
  • Browser and decompilation utility for easy debugging
  • Utility Objects for Expression Evaluation, Elaboration and Partial analysis
  • Highly customizable - error handler, user-defined attributes, user-defined meta comments, and more